Enhancement MOSFETs are widely used in digital integrated circuits (and require no bias circuitry in those applications). They also find applications in discrete- and integrated-circuit small-signal amplifiers. The figure below shows one way to bias a discrete enhancement NMOS for such an application. The resistor RS is used to provide feedback for bias-stabilization, in the same way that the emitter resistor does in a BJT bias circuit. The larger the value of RS, the less sensitive the bias point is to changes in MOSFET parameters caused by temperature changes or by device replacement. First the gate-to-ground voltage VG is found using the voltage divider rule as shown below: VG=(R2/(R1+R2))VDD Writing Kirchoff’s voltage law around the gate-to-source loop, we find: VGS=VG-ID.RS Writing Kirchoff’s voltage law around the drain-to-source loop, we find VDS=VDD-ID(RD+RS) ID can be written as ID=-(1/RS)VGS+VG/RS This equation is seen to be the equation of a straight line on the ID-VGS axes. It intercepts the ID-axis at VG/RS and the VG-axis at VG. The line can be plotted in the same set of axes as the transfer characteristics of the device, and the point of intersection locates the bias values of ID and VGS.