Clock skew demonstration

 
  • SYNCHRONOUS
  • CAPACITIVE
  • BUFFER
  • DIGITAL SOURCE
  • FLIPFLOP
comments powered by Disqus

Overview

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Circuit info

Author

Created on: 07 Nov 2013
<a href="http://www.docircuits.com/public-circuit/1607/clock-skew-demonstration" > Clock skew demonstration <a/>