The circuit uses three ICs namely: 7485 which is a 4-bit magnitude comparator, 74190 which is a up-down decade counter and 7447 which is a BCD to seven-segment decoder IC. The interconnections made within the circuit would illustrate the working of the display system. First, the input given by the user (after binary encoding) is given as input to the decade counter from the parallel input pins P0,P1,P2,P3. The parallel load pin PL is active low and therefore is given a logic ‘0’. The output from the decade counter is passed to the magnitude comparator which is compared with the input from the P0,P1,P2,P3 pins. The comparator has three outputs viz: greater than, lesser than, equal to. The comparison may be any of these three possibilities and therefore it is essential to decide whether to keep counting up or start counting down based on the comparator output. This decision circuitry is designed as a combinational circuit with the help of logic gates. As can be seen in the circuit, the two outputs from the logic circuit are CE and UD. These are respectively connected to the CE and U/D pin of the counter IC. The CE pin is active low and is called count enable, therefore the counter counts every time this pin receives a logic ‘0’. The U/D pin dictates whether the counter is in up-counter (logic ‘0’ at U/D pin) or down-counter (logic ‘1’ at U/D pin) mode respectively.
Finally, the output at each stage from the counter is given to the decoder IC that keeps displaying the corresponding floor number in the seven segment display.