DC biasing of an FET is done to produce the required gate-to-source voltage (VGS) to get the desired value of drain current (¬ID). Common-source configuration offers high input impedance, low output impedance, high voltage gain and the output voltage is 180? out-of-phase with the input voltage. The commonly used common-source biasing configurations include fixed-bias configuration, self-bias configuration and voltage-divider configuration. In this experiment we’ll use the fixed-bias configuration. The fixed-bias configuration is not used much as the wide differences in the minimum and maximum values of the JFET parameters make drain current levels unpredictable with simple fixed-bias circuits.